NovoBlox OTP Memory IP

NovoBlox® is a family of small, One-Time-Programmable (OTP) memory IP. NovoBlox is available in two architectures, Serial and ROM. Download our printable product brief here.  For more specific information a PDF version of the NovoBlox Short Form Catalog is available for download.

NovoBlox Serial Architecture OTP Memories

Each of the OTP memory cells has a maintained output. Unprogrammed cells are a logic zero. Programming and verification is completed via a serial interface, implemented as a bit shift register, to minimize on-chip busing and pin count.

Cells are programmed in parallel and the Done signal asserted when progamming is complete. Unprogrammed cells may be programmed in subsequent write cycles.

A preview mode transfers the pending write data from the shift register to the maintained outputs. This mode supports both factory test and trial values. Trial values can be used to find the optimum value for a circuit trim.

The Serial architecture features maintained outputs and a serial programming interface, making it ideal for fuse replacement.

Supported technologies:

• 180nm

• 130nm

• 90nm

NovoBlox ROM Architecture OTP Memories

The memory is word addressable with separate read, write and address buses. The clock is only required to write the memory.

Unprogrammed bits are zeros. All the bits in a word are programmed in parallel and the Done signal is asserted when programming is complete.

Unprogrammed bits in a word that has been written previously may be programmed in subsequent write cycles.

The ROM architecture is a natural fit for a processor based system.

Supported technologies:

• 180nm

• 130nm

• 90nm