Highest Reliability OTP Non-Volatile Memory

Novocell Smartbit

  • No area sacrificed to redundant bits

  • No need for ECC 

  • No "Lost" Tail Bits

  • ONLY NVM with Dynamic Programming 



 

 

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You are hereRegister for a individual Introduction to Smartbit OTP NVM Technology

Register for a individual Introduction to Smartbit OTP NVM Technology

Novocell is pleased to provide individual online webinars to explain how antifuse one-time programmable nonvolatile memory (OTP NVM) differs from other common NVM technologies like EEPROM, efuse, polyfuse, masked ROM, and other technologies.

Register for a no-obligation, no-strings-attached, webinar by simply providing your name and email address below, and we will email you to arrange a prospective date and time that will fit your schedule. 

We will even accomodate your team on the call, if that works best--just provide details to us in a follow up email. 

Thank you again for your interest. 

In the meantime, you may find value in reading our Smartbit Technology page, and downloading our technical brief. 

Webinar Request Form: 
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Last Name   :
Email   :
   

PARTNERSHIP PROGRAMS

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Supported Foundries:

TowerJazz

TSMC

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UMC

GlobalFoundries

SilTerra

Novocell Smartbit™ OTP Memory IP significantly reduces costs by implementing highly reliable antifuse technology in standard logic CMOS, without additional process steps.

The entire Smartbit-based OTP family avoids the data retention issues associated with floating gate memory. Unlike polysilicon or laser fuses, it is possible to route over Novobits, NovoBytes and NovoHD, thus consuming no additional chip area.

With the Novocell Smartbit design, our anti-fuse oxide breakdown high voltage is contained entirely within the bit cell itself, and supports programming at wafer, in package, or in circuit.

Learn more by downloading our detailed product information briefs and specifications PDF or contact us for a tailored presentation today!