NovoBlox OTP Memory Technology

It all begins with expertise, imagination and dedication...

NovoBlox® OTP Memory IP Features:

- Highly reliable antifuse technology

- Implements in standard Logic CMOS without additional process steps

- Breakdown voltage contained entirely in memory core

- Program at wafer, in package and in circuit

 

Novocell’s core technology is NovoBlox OTP (One-Time-Programmable) Memory IP. NovoBlox is implemented in a patented, silicon-proven, gate oxide antifuse technology yielding a highly reliable, non-volatile memory block.

While some memory IPs can only be programmed at the wafer level, NovoBlox can be programmed at the wafer, circuit level, or in the package. It can be implemented in standard Logic CMOS without additional process steps or post processing.

The NovoBlox SmartBit™ cell generates and confines the breakdown voltage entirely in the memory core allowing the unprogrammed cells to have the native reliability of the process while only the programmed cells see high voltage.

To ensure that a programmed cell has achieved hard breakdown, NovoBlox applies the high voltage until it detects the current signature of hard breakdown. 100 percent programmability and data retention are guaranteed.

NovoBlox avoids the data retention issues associated with floating gate designs. Unlike polysilicon or laser fuses, it is possible to route over NovoBlox thus consuming no additional chip area.